The semiconductor industry is continually reducing device dimensions in order to meet performance and packing density requirements. As device dimensions are decreased, however, contact geometries are also reduced and this results in an increase in parasitic contact resistance. For devices with submicron geometries, this increase in parasitic contact resistance is substantial and it degrades device performance. Several techniques have been proposed for forming electrical contacts with low contact resistance. A silicided electrical contact approach is one of the most promising techniques for reducing contact resistance. In this process, a metal silicide layer is placed between the contact surface and the overlying metallization to form an ohmic or low resistance electrical contact to the underlying contact surface. The formation of silicided electrical contacts to doped polysilicon surfaces, however, has proved to be a reliability issue. In particular, silicided electrical contacts often delaminate from doped polysilicon surfaces. If this delamination occurs an open circuit is formed and the device becomes non-functional. Accordingly, a need exists for a process that forms electrical contacts to doped polysilicon surfaces.